1. Field of the Invention
The present invention relates to an information processing apparatus adapted for dealing with a large amount of image-forming data in a printer controller, or the like.
2. Summary of the Related Art
FIG. 6 shows the schematic configuration of a printer 1 such as a laser printer, or the like, for performing page printing, which does not embody the present invention. This printer 1 has an image processing portion 5 for receiving print input data from a host side such as a personal computer, or the like, and converting the input data into output data configured so as to be able to be printed by a printing mechanism or engine 2 provided for performing printing on printing paper (or other appropriate recording medium) on the basis of the output data.
The image processing portion 5 includes an input interface circuit portion 11 for receiving input data from the host, a program storage ROM 15 which stores a program, or the like, for interpreting the input data and for converting the input data into output data for generating an image. The image processing portion 5 also includes a font storage ROM 16 which stores font bit map data to convert the input data into data allowed to be printed actually, and a DRAM 14 for storing the output data or storing intermediate data, or the like, generated in the middle of conversion of the input data into the output data. These constitutional parts are connected, through a bus 17, to a CPU 13 which controls conversion in accordance with the program stored in the ROM 15.
After the data input from the host is converted into output data in the image processing portion 5, the output data is supplied to the printing mechanism 2 through a video interface circuit portion 12 connected to the bus 17. As a result, printing is performed page-by-page.
The video interface circuit portion 12 is provided with an FIFO memory for temporarily storing DMA-transferred output data, and a shift register for converting parallel data outputted from the FIFO memory into serial data. Accordingly, the output data serialized in the raster direction is transferred to the printing mechanism 2. Further, control signals such as a command signal, a status signal, etc., can be exchanged between the CPU 13 of the image processing portion 5 and the printing mechanism 2 through the video interface circuit portion 12 so that the CPU 13 can control the printer 1 as a whole.
The image processing portion 5 having the ROMs 15 and 16, etc., connected to the bus 17 to which also the CPU 13 is connected, can be provided inexpensively if the CPU 13 can make direct access to the ROM 15, or the like, at a low speed. However, because it is impossible to use any high-throughput processor as the CPU 13, the image processing portion 5 is unsuitable for processing a large amount of data at a high speed.
Therefore, as shown in FIG. 7, a CPU 18 capable of operating at a high speed is used in a printer 1 for processing a large amount of data at a high speed. In the case where the CPU 18 operates with respect to low-operating-speed memories such as ROMs 15 and 16, etc., a system is employed in which the operating speed difference between the CPU 18 and the ROM 15, or the like, is absorbed by a memory controller 20 connected to the CPU 18 through a high-speed CPU bus 19.
In the image processing portion 6 shown in FIG. 7, the CPU bus 19 and the memory bus 17 connected to memories are independent of each other, so that internal processing can be made at a high speed by using the high-speed CPU 18. However, because the processing speed of the CPU 18 is dominated by the operating speed of memories such as DRAM 14, ROMs 15 and 16, etc., when access is made to these memories, the overall processing speed in the image processing portion 6 cannot be increased significantly despite the fact that the CPU 18 has a heightened operating frequency.
Although the processing speed of the DRAM 14 is relatively high compared with the processing speed of the ROMs 15 and 16, it is of greater importance to improve the input/output processing speed of the DRAM 14 in order to deal with a large amount of data in the image processing apparatus. A synchronous DRAM (hereinafter referred to as SDRAM) supplied with a synchronous clock pulse signal and capable of reading/writing data in accordance with the input clock has been developed so that, for example, the SDRAM can be operated at the same speed as that of the CPU 18 if the SDRAM is supplied with a clock pulse signal of the same operating frequency as that of the CPU 18. Accordingly, the operation of reading/writing a large amount of output data or intermediate data can be carried out at a high speed, so that the processing speed of the image processing portion 6 can be improved.
Because reading/writing is performed through the CPU 18 and the memory controller 20 even in the case where such an SDRAM is used as the DRAM 14, the time for processing in the memory controller 20 is required. Further, because not only the DRAM 14 but also the ROMs 15 and 16 and other interface portions are connected to the memory bus 17, the length of wiring for transmitting signals becomes large. Accordingly, the transmission speed becomes low and reflection as well as radiation noise of signal lines becomes large, so that the operating frequency is limited. Accordingly, the SDRAM capable of operating at the same speed as that of the CPU 18 cannot be utilized effectively.
It is therefore an object of the present invention to provide an image processing apparatus which is so high in processing speed as to be adapted for image processing in which a large amount of data are read-from/written-in a DRAM.
It is another object of the present invention to provide an image processing apparatus in which a large capacity of DRAM is set in the image processing apparatus so that a large amount of data can be inputted/outputted in a short time, and a CPU can make access to the DRAMs at a high speed.
It is a further object of the present invention to provide a printer using the aforementioned image processing apparatus to make image processing speed high to thereby perform high-resolution printing at a high speed.
Further, conversion of a large amount of input data into image-forming output data is required not only in the case of a printer but also in the case where an image is displayed on a display unit.
It is therefore a further object of the present invention to provide an information processing apparatus in which a large amount of data are processed in a short time so that the data can be written-in/read-from a large capacity of DRAM at a high speed.
According to the present invention, therefore, a RAM for storing a large amount of intermediate data or output data for image processing is connected not to a memory bus but to a CPU bus through which data can be directly read-from/written-into the CPU. That is, according to the present invention, an image processing apparatus is provided for converting input data into image-forming output data by using programs or font data stored in at least one ROM unit, and for outputting the image-forming output data. The image processing apparatus according to the present invention includes a CPU, at least one RAM unit for storing at least one of output data or intermediate data converted by the CPU, a memory controller for controlling access to the ROM unit and the RAM unit, a first bus to which the memory controller and the CPU are connected, and a second bus to which the memory controller and the ROM unit are connected. The RAM unit is connected to the first bus.
As described above, the RAM unit, which is capable of performing high-speed processing compared with ROM, is disposed in the vicinity of the CPU so that the CPU can access the RAM unit directly without going through the memory controller. Accordingly, the speed of processing between the CPU and the RAM unit can be improved greatly. Particularly in the image processing apparatus, input/output processing of output data or intermediate data with respect to the RAM unit occupies a large part of the content of processing. Accordingly, when this input/output processing time is shortened, the processing speed of the image processing apparatus as a whole can be improved greatly.
Further, when an SDRAM is utilized as the RAM unit connected to the first bus, the RAM unit can be operated by an operating clock signal which has the same operating frequency as is used in the CPU. Accordingly, reading/writing data from/into the RAM unit can be performed without reducing the processing speed of the CPU and without providing any wait state.
Further, in the image processing apparatus, a large amount of data are inputted into/outputted from the RAM unit. Accordingly, it is necessary to provide a plurality of RAM units. Therefore, when RAM units are connected to a third bus connected to the first bus through a bus driver, a high-speed stable operation can be carried out even in the case where a plurality of RAM units or a single large-capacity RAM unit is connected.
In the case where the processing speed of the CPU is further heightened so that the time of signal propagation through the bus driver becomes a problem, it is preferable that the RAM units are connected to the third bus which is connected to the first bus via a pipeline register. By use of the pipeline register, data having appeared in the third bus connected to the RAM units can be supplied to the first bus to which the CPU is connected in accordance with the clock signal after the passage of a predetermined time of one clock or more. As a result, while the apparent propagation delay time can be set between the RAM unit and the CPU, the length of wiring of each bus can be shortened by insertion of the pipeline register. Accordingly, the image processing apparatus is hardly affected by noise, so that high-speed data communication adapted to a high-speed CPU can be made between the CPU and the RAM unit.
This system in which the first and third buses are connected to each other through the pipeline register to exchange data between the CPU and the RAM unit is useful not only for the image processing apparatus but also for an information processing apparatus in which a large amount of data are read-from/written-into the RAM. Further, by use of the image processing apparatus having a CPU capable of performing high-speed data transfer between the CPU and the RAM unit, a large amount of input data for high-resolution color printing can be processed in a short time. This results in a printer which performs high-quality and high-speed printing.